Placement and CTS Techniques for High-performance Computing Designs
This paper discusses the challenges of designing high-performance computing (HPC) integrated circuits (ICs) to achieve maximum performance. The design process for HPC ICs has become more complex with each new process technology, requiring new architectures and design rules. The paper highlights how the Siemens Aprisa digital implementation solution can solve placement and clock tree challenges in HPC designs, which are fundamental to achieving desired performance metrics during place-and-route.
Aprisa's innovative architecture and patented technologies provide earlier confidence in the results due to its excellent correlation throughout the place-and-route flow, and with signoff tools, making it ideal for helping designers deliver HPC IC innovations faster. Also discussed are specific challenges affecting HPCs, such as tradeoffs between performance, power, and area metrics, and techniques available during clock tree synthesis to ensure HPCs meet their strict specifications.